1. Field of the Invention
The present invention relates to a BGA (Ball Grid Array) semiconductor device.
Priority is claimed on Japanese Patent Application No. 2010-143800, filed Jun. 24, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
When designing a system using a high-speed semiconductor device, such as when connecting a memory controller to multiple semiconductor memory devices, a fly-by topology is generally used in order to ensure the quality of waveforms. Regarding the fly-by topology, a command signal, an address signal, and a clock signal are supplied through one wire to each of the semiconductor memory devices.
Japanese Patent Laid-Open Publication No. 2009-75682 discloses a memory interface using the fly-by topology for connecting a memory controller and memory modules (DIMM). Specifically, regarding a clock signal CK, an address signal Add, and a command signal CMD, a memory controller 90 is connected by daisy chain to multiple SDRAM 92-1 to 92-n included in a DIMM module 91. Regarding a data signal DQ and a data strobe signal DQS, the memory controller 90 is connected by multiple wires to the respective SDRAM 92-1 to 92-n.
FIG. 26 illustrates a state in which multiple memory devices of a semiconductor device D are connected by daisy chain, i.e., in series to a memory controller C. In the case of the fly-by topology shown in FIG. 26, each memory device D includes multiple terminals on a surface thereof, and a terminal of one memory device D has to be connected by a signal wire to a corresponding terminal of an adjacent memory device D so that the memory devices D are connected in series. Thus, multiple signal wires are necessary.
However, when applying the fly-by topology shown in FIG. 26 to multiple command signals and address signals, the signal wires cross over one another on the same surface of a substrate, as shown in FIG. 27. FIG. 27 illustrates arrangement of terminals and connection of wires to the terminals on a surface of the semiconductor memory device D.
As shown in FIG. 27, multiple terminals T, T′, and T″ are provided on a rear surface of the semiconductor device D. Wires F are provided on an upper surface side of the semiconductor device D. The wires F extend in the right and left direction. The wires F are connected to the respective terminals T. Wires W0 extend only in the right direction. The wires W0 are connected to the respective terminals T′.
Although only one semiconductor device D is shown in FIG. 27, another semiconductor device D is positioned adjacent to the illustrated semiconductor device D. The wires F extend in the horizontal direction of FIG. 27 and are connected to terminals on the right and/or left adjacent semiconductor devices D. In other words, the fly-by wires F, which are connected to the respective terminals (balls) T positioned on the right side of the surface of the semiconductor device D, are connected to corresponding terminals (balls) on the adjacent semiconductor device D, to a memory controller C, or to a termination resistor Rt shown in FIG. 26.
Although not shown, the wires W0, which are connected to the terminals (balls) T′ positioned on the left side of the surface of the semiconductor device D, are connected to terminals on a right adjacent semiconductor device D. However, the wires W0 cannot extend in the right direction of FIG. 27 as indicated by a dashed line X, though the wires W0 extend straight in the left direction. For this reason, the wires W0 cross over the fly-by wires F on the substrate surface.
Currently, the limited number of wires can be provided between the terminals T″ on the left side and the terminal T″ on the right side, which are not positioned in the same horizontal line (not shown). For this reason, fly-by connection of the left and right terminals T″ cannot be achieved using only wires provided on the upper surface of the semiconductor device mounting board. To enable the fly-by topology, main wires have to be provided on an internal layer of a multi-layered substrate B, and vias V have to be provided close to signal terminals on the rear surface of each semiconductor device, as shown in FIGS. 28 to 30.
FIG. 28 is a plan view illustrating a fly-by topology in which fly-by wires on an upper surface of a multi-layered substrate are connected to main wires on an internal layer or on a rear surface of the multi-layered substrate. FIG. 29 is a cross-sectional view illustrating the wires on the internal layer of the multi-layered substrate shown in FIG. 28. FIG. 30 is a plan view illustrating an upper surface of a module including wires connected as shown in FIGS. 28 and 29.
As shown in FIGS. 28 to 30, fly-by wires are provided on an inner layer of a multi-layered substrate B so as to be connected to terminals through vias V near the terminals. In this case, a wire F01 on a surface layer, which extends from the terminal T of the semiconductor device D (D00, D01, and the like) to a via V, is a stub wire S.
The stub (branching) portions of the wire F01 are shown in FIG. 28. The stub (branching) portions of the via V are shown in FIG. 29. The length of the wire F01 on the surface layer, which is part of the stub wire, can be maximally shortened in a system including a multi-layered substrate.
A system requiring lower costs, such as digital consumer electronics, uses a four-layered substrate. For the four-layered substrate, however, it is difficult to shorten the length of the wire F01 between the terminal to the via V, which is part of a stub wire.
Regarding the four-layered substrate, it is general to provide ground planes in the second and third layers in consideration of signal integrity that indicates how properly a signal waveform of a digital signal is transmitted. For this reason, fry-by wires cannot be provided on the second and third layers, and therefore all fly-by wires have to be provided on a rear surface of the substrate, which is the side on which no semiconductor substrate is mounted. In this case, adjacent wires have to be distanced from each other by a value greater than defined by the design rule of the substrate, in consideration of crosstalk noises. Accordingly, the length of the stub wire (i.e., the stub length) between a via and a terminal of the semiconductor device including the four-layered substrate becomes larger than that of a semiconductor device including a substrate with the greater number of layers in which fly-by wires can be provided on the second and third layers.
As the stub length increases, the signal integrity further degrades due to the effect of reflective noises. Particularly when the data rate of the transmission signal is set to be greater, the signal integrity further degrades due to reflection.